1. Field of the Invention
The present invention provides a method of making a local interconnect in an embedded memory, more particularly, a method to decrease the resistance of the local interconnect in the embedded memory.
2. Description of the Prior Art
In the semiconductor industry, the increase in process integrity has led to the formation of an embedded memory by linking a memory array to a logic circuit. More specifically, both the memory cell array and the high-speed logic circuit elements are integrated onto the same chip to produce an embedded memory. An isolation layer is formed between every device and the circuit to avoid shorting the circuit, followed by the formation of a plurality contact holes in the isolation layer via a photo-etching-process (PEP). Finally, a conducting layer is filled into the contact hole to produce an electrical interconnection. between each metal-oxide-semiconductor (MOS) transistor and the circuit.
Please refer to FIG. 1 to FIG. 8 of the schematic diagrams of a prior art method of making a landing via of an embedded memory in a semiconductor wafer 10. As shown in FIG. 1, both a memory array area 12 and a periphery circuit area 14 are defined on the surface of a silicon base 16 of the semiconductor wafer 10. The memory array area 12 comprises a cell-well 18, and the periphery circuit area 14 comprises an N-well 20 and at least one P-well 22. In the prior art, a plurality of gates 24,26,28 are simultaneously formed in both the memory array area 12 and in the periphery circuit area 14, with spacers 30 surrounding either side of the gates 24,26,28, and a lightly doped drain (LDD) 32 located adjacent to the gates 24,26,28. As well, a source 34 and a drain 36 are formed adjacent to both the gate 26 and gate 28.
As shown in FIG. 2, a dielectric layer 38 is formed on the surface of the semiconductor wafer 10 as a silicon dioxide layer. And as shown in FIG. 3, a PEP process is then performed to define several thin metal connection regions 40. Then, as shown in FIG. 4, a second PEP process is used to define the first, second and third contact windows, 44,42,46, respectively, in the dielectric layer 38. The first contact window 44 is used to contact with the capacitor. The second contact window 42 is used to contact with the bit line, also known as the landing via. The third contact window 46 functions as a source or drain and connects with a strip contact in the periphery circuit area 14. The depths of the first, second, and the third contact windows 44,42,46 are all equal, and therefore all horizontally aligned.
As shown in FIG. 5, a PEP process is performed to form a fourth contact window 48 in the dielectric layer 38. The fourth contact window 48 is located in the strip contact of the periphery circuit area 14 and is used to connect with the gate region. Since the fourth contact window 48 has a shallower depth than the three other contact windows 44,42,46, it is not horizontally aligned with the contact windows 44,42,46. The third contact window 46 and the fourth contact window 48 separately connect with the gate, source, and drain regions of different transistors, and are therefore on different vertical planes. Next, as shown in FIG. 6, a barrier layer 50 and a dielectric layer 52 are formed, respectively, on the silicon base 16. The barrier layer 50 and the dielectric layer 52 may be composed of titanium nitride and tantalum oxide, respectively.
As shown in FIG. 7, a photoresist layer (not shown) is used as a mask to etch the dielectric layer 52 so that the dielectric layer 52 only exists in the area of the second contact window 42 and the metal contact area 40 of the memory array area 12. As shown in FIG. 8, a metal layer 54 is then deposited on the surface of the silicon base 16, to fill in the contact windows 42,44,46,48 and the metal contact areas 40. Finally, the dielectric layer 38 is used as a stop layer to produce a uniform metal layer 54.
In the above method of making the local interconnect of the embedded memory, the difference in depth between the memory array area and the periphery circuit area, requires the separate creation of the landing via and local interconnect. Thus, at least four photomasks are needed in the process, which is both complicated and costly. Also, a conducting layer is filled in between each landing via and local interconnect as conducting material, increasing the contact resistance while decreasing the electrical conductance.
It is therefore a primary objective of the present invention to provide a method to create a local interconnect in an embedded memory that simplifies the complexity of process, decreases cost, and effectively decreases resistance.
The method of the present invention first defines a memory array area and a periphery circuit area on the surface of a semiconductor wafer. Then, a plurality of gates and lightly doped drains (LDD) are separately formed in the memory array area and in the periphery circuit area. Next, a silicon nitride layer and a dielectric layer are formed, respectively, on the semiconductor wafer and on the surface of each gate. A plurality of landing via holes and local interconnect holes are then separately formed in the dielectric layer in the memory array area and the periphery circuit area. Next, an electrical conducting layer is filled into each hole to form the landing via and the local interconnect. Both the dielectric layer and a portion of the silicon nitride layer in the periphery circuit area are removed to form a spacer one either side of the gate in the periphery circuit area. Finally, a metal silicide layer is formed on the surfaces of the gates and the local interconnect in the periphery circuit area as well as on the top surface of the landing via in the memory array area.
Since the method of the present invention simultaneously forms each landing via and local interconnect, only a single photo mask is required in the entire process. As well, the formation of a silicide layer on the top surface of each landing via and on the surface of each local interconnect in the periphery circuit area decreases the resistance and improves the electrical performance of the embedded memory.